The present invention relates to a semiconductor device and a manufacturing technology thereof, in particular, to a technology effective when applied to the manufacture of a semiconductor device using a dual damascene process for forming a fine Cu wiring in an interlayer insulating film on a semiconductor substrate.
With miniaturization and speed-up of LSI (large-scale integrated circuit), instead of conventionally used Al (aluminum), Cu (copper) having less electrical resistance has come to be used frequently as a wiring material of LSI.
However, a reaction rate of Cu with a plasma ion is so low that a sufficient productivity cannot be achieved when Cu wirings are formed by etching. A damascene process has therefore been used in the formation step of Cu wirings. This is a technology of forming a wiring trench in an interlayer insulating film, depositing a Cu film on the interlayer insulating film and in the wiring trench, and then polishing/removing the Cu film on the interlayer insulating film by chemical mechanical polishing to form a Cu wiring in the wiring trench.
In addition, since Cu is likely to be diffused in the interlayer insulating film so that the Cu wiring formed in the wiring trench should be covered around with a diffusion preventive film (barrier film). As the barrier film for covering the upper surface of the Cu wiring, an insulating film-based barrier film (liner film) is typically used. This liner film is also used as a portion of the interlayer insulating film on the Cu wiring. On the other hand, as a barrier film for covering the side walls and the bottom surface of the wiring trench, a metal-based barrier film (barrier metal film) is used. The barrier metal is formed in the wiring trench of the interlayer insulating film so that it is used as a portion of the wiring material.
The damascene process includes a single damascene process of simply forming a Cu wiring in a wiring trench and a dual damascene process of forming a wiring trench and a via hole in an interlayer insulating film successively and then burying a Cu film in the wiring trench and the via hole concurrently. Of these, the dual damascene process can simplify a formation step of Cu wirings so that it has been used frequently in a manufacturing step of a semiconductor device having a multilayer Cu wiring.
Description on the Cu wiring formation technology using the above-described dual damascene process can be found in Patent Documents 1 to 3.
The dual damascene process described in Patent Document 1 (Japanese Patent Laid-Open No. 2006-245236) includes the steps of: forming, on an insulating layer formed on a semiconductor substrate, a first film to be etched; forming a first mask film having an opening on the first film to be etched; forming, on the first mask film, a second film to be etched so as to fill the opening portion therewith; forming a second mask film on the second film to be etched; forming a wiring pattern in the second mask film located above the opening portion; with the second mask film as a mask, etching the second film to be etched to form a wiring pattern from the bottom of which the first mask film is exposed and, with the first mask film exposed from the bottom of the wiring pattern as a mask, etching the first film to be etched to form a via pattern in the first film to be etched; and selectively etching the insulating layer by using the wiring pattern and the via pattern to form a via hole in the insulating layer and at the same time, form a wiring trench above the via hole.
According to this document, the first and second films to be etched are removed selectively by the same etching step with the first and second mask films as masks and the wiring pattern and the via pattern are formed on the insulating layer simultaneously with high precision so that this process can form a dual damascene structure having a fine wiring structure with high precision.
The dual damascene process described in Patent Document 2 (Japanese Patent Laid-Open No. 2006-294771) is characterized by that it is equipped with a step of forming, on an insulating film, a first mask so as to have a wiring trench pattern, a step of forming, on the first mask, a second mask so as to have a connection hole pattern, and a step of forming a wiring trench and a connection hole in the insulating film with the first mask and the second mask; in the step of forming a wiring trench and a connection hole in the insulating film with the first mask and the second mask, the connection hole is formed first in the insulating film; and the connection hole pattern is formed in a direction intersecting the arrangement direction of the wiring trench pattern and at the same time, the end portion of the connection hole pattern is formed on a portion of the first mask.
According to this process, a margin of the connection hole pattern in lithography is secured and the first mask having a wiring trench pattern formed therein determines the position of the arranging direction of the wiring trench in self alignment so that misalignment does not occur and connection hole patterns can be formed densely in the arrangement direction of wiring trenches.
Patent Document 3 (Japanese Patent Laid-Open No. 2002-319617) discloses a technology of, in forming a wiring trench and a via hole in an interlayer insulating film covering the upper portion of a first wiring layer therewith, etching an upper portion of the via hole reaching the bottom of the wiring trench into a tapered shape in order to suppress it from overhanging during embedding a second wiring layer and thus, preventing formation of voids.    Patent Document 1: Japanese Patent Laid-Open No. 2006-245236    Patent Document 2: Japanese Patent Laid-Open No. 2006-294771    Patent Document 3: Japanese Patent Laid-Open No. 2002-319617